OpenOCD performs the check and gives an error if the expected output and read output don't match. Expected output sequence at TDO is defined by TDO and MASK instructions. The SMASK set to all ones represents importance of the bits. Shift 64 bits (2 x size of the IDCODE register) of ones (F.FF)throughout the JTAG chain while in the SHIFT-DR state. So it's a good practice to put them before SDR and SIR instructions. Without HDR, TDR, TIR, HIR instructions, OpenOCD can generate errors depending on the present state. HDR and TDI set to zero indicate that there are no other devices in the chain except given. At the RESET state, the IDCODE register (if such exists) is set as data register by default The scanned out 33-bit long sequence will consist of ID code and an extra bit at MSB position: "0x 1 ?5045093".Īll explanations are given in the comments, read them carefully: Similarly to option (2), but now PROM will be loaded with IDCODE instruction and Spartan 3E will be bypassed.Shift a 32+1 bit long sequence into TDI while in " ShiftDR" state, at the TDO output observe ID code of Spartan 3E padded with an extra bit at LSB position: "0x163820126" (see the explanation in the code below). ID code register will be selected as Spartan 3E's data register and a 1-bit long bypass register will selected as PROM's data register. Load Spartan 3E's instruction register with IDCODE instruction, and load PROM's instruction register with BYPASS instruction.Shift any 64-bit long sequence into TDI while in " ShiftDR" state and observe concatenated pair of ID codes = "0x ?1C10093?5045093" at TDO. According to JTAG specifications, all devices in the chain must choose ID code register as data register. " /opt/Xilinx/10.1/ISE/".įrom the " xc3s100e.bsd" and " xcf02s.bsd" we can learn the Instruction Register lengthsįound Device ID : 11C10093 # Spartan 3E, XC3S100E If you have Xilinx ISE already installed, check out the " xc3s100e.bsd" file located at " $XILINX_ISE_PATH/spartan3e/data/ " and " xcf02s.bsd" file located at " $XILINX_ISE_PATH/xcf/data/", where $XILINX_ISE_PATH is the installation path, e.g. These files can be retrieved from the vendor's website or from the Xilinx ISE installation. For each chip, JTAG-specific instructions and properties of special registers including BSR (boundary scan register) are provided in BSDL files. The second chip ( xcf02s) is a flash memory (PROM). The first IC ( xc3s100e) is the actual FPGA chip from the Spartan 3E family. Here is the JTAG chain of the Digilent Basys2 FPGA board: A generic FTDI-MPSSE-based JTAG adapter was used and the tests were conducted in OpenOCD. This tutorial concerns with explaining use of some basic Serial Vector Format (SVF) instructions assuming that you are familiar with JTAG and TAP.Īs an example, reading ID codes of the devices in a JTAG chain of the Digilent Basys2 FPGA board is given.
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